The present invention relates generally to integrated circuit testing, and more specifically, to a performance-screen ring oscillator (PSRO) using an integrated circuit test signal distribution network.
High-speed testing may be used to screen integrated circuits for basic device speed and health-of-technology metrics. For a microprocessor integrated circuit design, it is possible to carry out high-speed testing of the die on-wafer to get an idea of how fast the processor can run before investing the resources to package the design. Further high-speed testing may also be performed after the design is packaged. High-speed testing may require relatively complex, expensive equipment, and it may be difficult to pinpoint the root cause of any issued detected by such testing.
High-speed testing may be performed by placing performance-screen ring Oscillators (PSROs) at various points on the integrated circuit, for example, in a kerf region. The oscillation frequency can be read out from the PSROs on the integrated circuit, giving a direct measurement of the device performance at different points on the integrated circuit. However, PSRO structures may require a relatively large amount of space on the integrated circuit, and, depending on placement, may not give accurate data as to the performance of the integrated circuit.